Difference between revisions of "X86 Todo List"
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					 (Created page with '= Highest priority = * Flesh out and debug 64-bit modern ISA (what's needed by users) * Complete x87 support * AVX support * Performance correlation ** With real hardware and/or …')  | 
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= Highest priority =  | = Highest priority =  | ||
* Flesh out and debug 64-bit modern ISA (what's needed by users)  | * Flesh out and debug 64-bit modern ISA (what's needed by users)  | ||
| − | *   | + | * FS-mode core timing issues  | 
| − | *   | + | ** Debug TimingSimpleCPU issues?  | 
| + | ** In-order pipeline core model support  | ||
| + | ** Out-of-order core model (O3) support  | ||
| + | * Multiprocessor timing support: need to enforce atomicity of locked load/op/store sequences in timing cache models  | ||
| + | ** Ruby and M5 classic?  | ||
* Performance correlation  | * Performance correlation  | ||
** With real hardware and/or existing correlated simulator  | ** With real hardware and/or existing correlated simulator  | ||
** Micro-op counts for functional implementation  | ** Micro-op counts for functional implementation  | ||
** Timing for out-of-order core (requires O3 support)  | ** Timing for out-of-order core (requires O3 support)  | ||
| − | *   | + | * Complete x87 support  | 
| − | *   | + | * AVX support  | 
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
= Useful but not strictly necessary =  | = Useful but not strictly necessary =  | ||
| Line 26: | Line 25: | ||
= Could be done but might never happen =  | = Could be done but might never happen =  | ||
* other OS support (OSX, Windows, ??)  | * other OS support (OSX, Windows, ??)  | ||
| − | *   | + | * complete real mode support  | 
| − | |||
| − | |||
Latest revision as of 01:49, 4 May 2010
Contents
Highest priority
- Flesh out and debug 64-bit modern ISA (what's needed by users)
 -  FS-mode core timing issues
- Debug TimingSimpleCPU issues?
 - In-order pipeline core model support
 - Out-of-order core model (O3) support
 
 -  Multiprocessor timing support: need to enforce atomicity of locked load/op/store sequences in timing cache models
- Ruby and M5 classic?
 
 -  Performance correlation
- With real hardware and/or existing correlated simulator
 - Micro-op counts for functional implementation
 - Timing for out-of-order core (requires O3 support)
 
 - Complete x87 support
 - AVX support
 
Useful but not strictly necessary
- Split up ISA output for faster compiling
 - Improve ISA description language support for x86
 
To do eventually but not right away
- ACPI support
 - KVM-based fast functional CPU model
 - Virtualization extensions support (AMD SVM, etc.)
 
Could be done but might never happen
- other OS support (OSX, Windows, ??)
 - complete real mode support