Difference between revisions of "Google Summer of Code"
From gem5
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=== Finding Help & Getting Things Done === | === Finding Help & Getting Things Done === | ||
| − | === Mentors === | + | === Mentors / M5 Simulation Team === |
| − | + | * Steve Reinhardt (Ph.D, Univ. of Michigan) - Simulator Infrastructure; ISA description; Full System Simulation | |
| − | + | * Nate Binkert (Ph.D, Univ. of Michigan) - Parallel Simulation; Networking Models; Configuration Scripts | |
| + | * Ali Saidi (M.S., Univ. of Michigan) - Simulator Infrastructure; Full System Simulation | ||
| + | * Lisa Hsu (M.S., Univ. of Michigan) - Full System Workloads; Memory Modeling; Checkpointing Simulations | ||
| + | * Kevin Lim (M.S., Univ. of Michigan) - CPU Modeling (Out-of-Order, SimpleCPU) ; Full-System Simulation; | ||
| + | * Gabe Black (M.S., Univ. of Michigan) - ISA description (SPARC, x86); Simulator Infrastructure; Full System Simulation | ||
| + | * Korey Sewell (M.S., Univ. of Michigan) - ISA description (MIPS); Out-of-Order CPU Modeling; SMT Simulation | ||
| + | * Ron Dreslinski (M.S., Univ. of Michigan) - Memory Modeling | ||
Revision as of 20:27, 11 March 2008
Contents
Introduction
Project Ideas
All the ideas listed here will require some familiarity with Python and a good grasp of advanced C++ concepts.
- Build a direct execution CPU model based on the Linux Kernel Virtual Machine
- Parallelize M5
- Use the Wisconsin Wind Tunnel as a guide
- This actually isn't as bad as it sounds as all objects schedule their own events and there are limited ways they can interact with other objects in the system.
- Memory network models
- (e.g. Crossbar or Mesh)
- Directory Protocol
- Real In-order core model
- There is code to start with but nothing that is fully fleshed out.
- Write a PLI interface to connect Verilog CPUs to the memory system.
- Sampling/fast-forwarding techniques
- This would have the most impact if it was coupled with (1)
- Using SMARTS work would be a good guide
- Flash memory device model (seems popular nowadays)
- This could be a hard drive based model like we're seeing in laptops now or a memory device model like several research papers have suggested as storage in between DRAM and disk.
Finding Help & Getting Things Done
Mentors / M5 Simulation Team
- Steve Reinhardt (Ph.D, Univ. of Michigan) - Simulator Infrastructure; ISA description; Full System Simulation
- Nate Binkert (Ph.D, Univ. of Michigan) - Parallel Simulation; Networking Models; Configuration Scripts
- Ali Saidi (M.S., Univ. of Michigan) - Simulator Infrastructure; Full System Simulation
- Lisa Hsu (M.S., Univ. of Michigan) - Full System Workloads; Memory Modeling; Checkpointing Simulations
- Kevin Lim (M.S., Univ. of Michigan) - CPU Modeling (Out-of-Order, SimpleCPU) ; Full-System Simulation;
- Gabe Black (M.S., Univ. of Michigan) - ISA description (SPARC, x86); Simulator Infrastructure; Full System Simulation
- Korey Sewell (M.S., Univ. of Michigan) - ISA description (MIPS); Out-of-Order CPU Modeling; SMT Simulation
- Ron Dreslinski (M.S., Univ. of Michigan) - Memory Modeling
